This invention relates to a memory of high density, and more particularly to a dynamic memory which employs MOS transistors (hereinbelow, termed "MOSTs").
In a prior-art dynamic memory employing MOSTs, a memory cell consists of one N-channel MOST and a capacitance for storing charges as is connected to the MOST. With the progress of the semiconductor integrated circuit technology, it has been requested to render the size of a memory cell smaller and smaller. As the size of the memory cell becomes smaller, the amplitude of a signal which is read out from the memory cell decreases more. Accordingly, a sense amplifier for detecting the signal from the memory cell has been requested to become increasingly high in performance and has inevitably resulted in occupying a large space. In the prior art, a large number of memory cells are connected to a pair of data lines, to which a sense amplifier for differentially amplifying voltages on these data lines is connected. A large number of such structural units are juxtaposed to construct the memory. In such prior-art memory, the size of the sense amplifier is larger than that of the memory cell. Therefore, even when the memory cell size is reduced, the interval of the data lines which are connected to different sense amplifiers cannot be made smaller. For this reason, it is difficult to array a larger number of memory cells on a single semiconductor substrate. Especially in case where the memory cell of smaller size is to be employed as described above, it is requested to enhance the performance of the sense amplifier, and it is therefore impossible to make the size of the sense amplifier small. Accordingly, the interval of the data lines cannot be reduced even when the memory cell size is made small.